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16-bit, 500 ksps pulsar ? dual, 2-channel, simultaneous sampling adc ad7654 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features dual, 16-bit, 2-channel simultaneous sampling adc 16-bit resolution with no missing codes throughput: 500 ksps (normal mode) 444 ksps (impulse mode) inl: 3.5 lsb max (0.0053% of full scale) snr: 89 db typ @ 100 khz thd: ?100 db @ +100 khz analog input voltage range: 0 v to 5 v no pipeline delay parallel and serial 5 v/3 v interface spi?/qspi?/microwire?/dsp compatible single 5 v supply operation power dissipation: 120 mw typical 2.6 mw @ 10 ksps packages: 48-lead low profile quad flat package (lqfp) 48-lead lead frame chip scale package (lfcsp) low cost applications ac motor control 3-phase power control 4-channel data acquisition uninterrupted power supplies communications functional block diagram control logic and calibration circuitry a/b 16 d[15:0] busy cs ser/par ognd ovdd dgnd d v dd serial port byteswap rd a v dd a gnd refx refgnd pd reset cnvst inan switched cap dac ad7654 ina1 impulse mux eoc ina2 a0 inb1 inbn inb2 track/hold 2 parallel interface 03057-001 clock mux mux figure 1. table 1. pulsar selection type/ksps 100 to 250 500 to 570 800 to 1000 >1000 pseudo differential ad7660/ ad7661 AD7653 ad7650/ ad7652 ad7664/ ad7666 ad7667 true bipolar ad7663 ad7665 ad7671 true differential ad7675 ad7676 ad7677 ad7621 ad7623 18-bit ad7678 ad7679 ad7674 ad7641 multichannel/ simultaneous ad7654 ad7655 general description the ad7654 is a low cost, simultaneous sampling, dual- channel, 16-bit, charge redistribution sar, analog-to-digital converter that operates from a single 5 v power supply. it contains two low noise, wide bandwidth, track-and-hold amplifiers that allow simultaneous sampling, a high speed 16-bit sampling adc, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. each track-and-hold has a multiplexer in front to provide a 4-channel input adc. the a0 multiplexer control input allows the choice of simultaneously sampling input pairs ina1/inb1 (a0 = low) or ina2/inb2 (a0 = high). the part features a very high sampling rate mode (normal) and, for low power applications, a reduced power mode (impulse) where the power is scaled with the throughput. operation is specified from ?40c to +85c. product highlights 1. simultaneous sampling. the ad7654 features two sample-and-hold circuits that allow simultaneous sampling. it provides inputs for four channels. 2. fast throughput. the ad7654 is a 500 ksps, charge redistribution, 16-bit sar adc with internal error correction circuitry. 3. superior inl and no missing codes. the ad7654 has a maximum integral nonlinearity of 3.5 lsb with no missing 16-bit codes. 4. single-supply operation. the ad7654 operates from a single 5 v supply. in impulse mode, its power dissipation decreases with throughput. 5. serial or parallel interface. versatile parallel or 2-wire serial interface arrangement is compatible with both 3 v and 5 v logic.
ad7654 rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 specifications..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings............................................................ 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 terminology .................................................................................... 11 typical performance characteristics ........................................... 12 application information................................................................ 14 circuit information.................................................................... 14 modes of operation ................................................................... 14 transfer functions...................................................................... 14 typical connecti on diagram ................................................... 16 analog inputs.............................................................................. 16 input channel multiplexer........................................................ 16 driver amplifier choice ........................................................... 16 voltage reference input ............................................................ 17 power supply............................................................................... 17 power dissipation....................................................................... 17 conversion control ................................................................... 18 digital interface.......................................................................... 18 parallel interface......................................................................... 18 serial interface ............................................................................ 20 master serial interface............................................................... 20 slave serial interface .................................................................. 22 microprocessor interfacing....................................................... 24 spi interface (adsp-219x) ....................................................... 24 application hints ........................................................................... 25 layout .......................................................................................... 25 evaluating the ad7654 performance ...................................... 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 27 revision history 11/05rev. a to rev. b changes to general description .................................................... 1 changes to timing specifications .................................................. 5 changes to figure 16...................................................................... 13 changes to figure 18...................................................................... 15 added table 8.................................................................................. 17 changes to figure 24...................................................................... 19 changes to figure 29...................................................................... 21 updated outline dimensions ....................................................... 26 changes to ordering guide .......................................................... 26 11/04rev. 0 to rev. a changes to figure 7........................................................................ 12 changes to figure 18...................................................................... 15 changes to figure 19...................................................................... 16 changes to voltage reference input section .............................. 17 changes to conversion control section..................................... 18 changes to digital interface section ........................................... 18 updated outline dimensions...................................................... 25 11/02revision 0: initial version
ad7654 rev. b | page 3 of 28 specifications avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v; all specifications t min to t max , unless otherwise noted. table 2. parameter conditions min typ max unit resolution 16 bits analog input voltage range v inx C v inxn 0 2 v ref v common-mode input voltage v inxn ?0.1 +0.5 v analog input cmrr f in = 100 khz 55 db input current 500 ksps throughput 45 a input impedance 1 throughput speed complete cycle in normal mode 2 s throughput rate in normal mode 0 500 ksps complete cycle in impulse mode 2.25 s throughput rate in impulse mode 0 444 ksps dc accuracy integral linearity error 2 ?3.5 +3.5 lsb 3 no missing codes 16 bits transition noise 0.7 lsb full-scale error 4 t min to t max 0.25 0.5 % of fsr full-scale error drift 4 2 ppm/c unipolar zero error 4 t min to t max 0.25 % of fsr unipolar zero error drift 4 0.8 ppm/c power supply sensitivity avdd = 5 v 5% 0.8 lsb ac accuracy signal-to-noise f in = 20 khz 88 90 db 5 f in = 100 khz 89 db spurious-free dynamic range f in = 100 khz 105 db total harmonic distortion f in = 100 khz ?100 db signal-to-noise and distortion f in = 20 khz 87.5 90 db f in = 100 khz 88.5 db f in = 100 khz, ?60 db input 30 db channel-to-channel isolation f in = 100 khz ?92 db ?3 db input bandwidth 10 mhz sampling dynamics aperture delay 2 ns aperture delay matching 30 ps aperture jitter 5 ps rms transient response full-scale step 250 ns reference external reference voltage range 2.3 2.5 avdd/2 v external reference current drain 500 ksps throughput 180 a digital inputs logic levels v il ?0.3 +0.8 v v ih +2.0 dvdd + 0.3 v i il ?1 +1 a i ih ?1 +1 a
ad7654 rev. b | page 4 of 28 parameter conditions min typ max unit digital outputs data format 6 pipeline delay 7 v ol i sink = 1.6 ma 0.4 v v oh i source = ?500 a ovdd ? 0.2 v power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 8 v operating current 9 500 ksps throughput avdd 15.5 ma dvdd 8.5 ma ovdd 100 a power dissipation 500 ksps throughput 9 120 135 mw 10 ksps throughput 10 2.6 mw 444 ksps throughput 10 114 125 mw temperature range 11 specified performance t min to t max ?40 +85 c 1 see the analog inputs section. 2 linearity is tested using endpoints, not best fit. 3 lsb means least significant bi t. within the 0 v to 5 v input range, one lsb is 76.294 v. 4 see the terminology section. these specifications do not include the error contribution from the external reference. 5 all specifications in db are referred to as full-scale input, fs; tested with an input signal at 0.5 db below full scale unles s otherwise specified. 6 parallel or serial 16-bit. 7 conversion results are available imme diately after completed conversion. 8 the maximum should be the minimum of 5.25 v and dvdd + 0.3 v. 9 in normal mode; tested in parallel reading mode. 10 in impulse mode; tested in parallel reading mode. 11 consult sales for extended temperature range.
ad7654 rev. b | page 5 of 28 timing specifications avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v; all specifications t min to t max , unless otherwise noted. table 3. parameter symbol min typ max unit conversion and reset (see figure 22 and figure 23 ) convert pulse width t 1 5 ns time between conversions (normal mode/impulse mode) t 2 2/2.25 s cnvst low to busy high delay t 3 32 ns busy high all modes except in master serial read after convert mode (normal mode/impulse mode) t 4 1.75/2 s aperture delay t 5 2 ns end of conversions to busy low delay t 6 10 ns conversion time (normal mode/impulse mode) t 7 1.75/2 s acquisition time t 8 250 ns reset pulse width t 9 10 ns cnvst low to eoc high delay t 10 30 ns eoc high for channel a conversion (normal mode/impulse mode) t 11 1/1.25 s eoc low after channel a conversion t 12 45 ns eoc high for channel b conversion t 13 0.75 s channel selection setup time t 14 250 ns channel selection hold time t 15 30 ns parallel interface modes (see figure 24 to figure 28 ) cnvst low to data valid delay t 16 1.75/2 s data valid to busy low delay t 17 14 ns bus access request to data valid t 18 40 ns bus relinquish time t 19 5 15 ns a/ b low to data valid delay t 20 40 ns master serial interface modes (see figure 29 and figure 30 ) cs low to sync valid delay t 21 10 ns cs low to internal sclk valid delay 1 t 22 10 ns cs low to sdout delay t 23 10 ns cnvst low to sync delay (read during convert) (normal mode/impulse mode) t 24 250/500 ns sync asserted to sclk first edge delay t 25 3 ns internal sck period 2 t 26 23 40 ns internal sclk high 2 t 27 12 ns internal sclk low 2 t 28 7 ns sdout valid setup time 2 t 29 4 ns sdout valid hold time 2 t 30 2 ns sclk last edge to sync delay 2 t 31 1 ns cs high to sync hi-z t 32 10 ns cs high to internal sclk hi-z t 33 10 ns cs high to sdout hi-z t 34 10 ns busy high in master serial read after convert 2 t 35 see table 4 cnvst low to sync asserted delay (normal mode/impulse mode) t 36 0.75/1 s sync deasserted to busy low delay t 37 25 ns
ad7654 rev. b | page 6 of 28 parameter symbol min typ max unit slave serial interface modes (see figure 32 and figure 33 ) external sclk setup time t 38 5 ns external sclk active edge to sdout delay t 39 3 18 ns sdin setup time t 40 5 ns sdin hold time t 41 5 ns external sclk period t 42 25 ns external sclk high t 43 10 ns external sclk low t 44 10 ns 1 in serial interface modes, the sync, sclk, an d sdout timings are defined with a maximum load c l of 10 pf; otherwise c l is 60 pf maximum. 2 in serial master read during co nvert mode. see table 4 for serial master read after convert mode. table 4. serial clock timings in master read after convert divsclk[1] 0 0 1 1 divsclk[0] symbol 0 1 0 1 unit sync to sclk first edge delay minimum t 25 3 17 17 17 ns internal sclk period minimum t 26 25 50 100 200 ns internal sclk period typical t 26 40 70 140 280 ns internal sclk high minimum t 27 12 22 50 100 ns internal sclk low minimum t 28 7 21 49 99 ns sdout valid setup time minimum t 29 4 18 18 18 ns sdout valid hold time minimum t 30 2 4 30 80 ns sclk last edge to sync delay minimum t 31 1 3 30 80 ns busy high width maximum (normal) t 35 3.25 4.25 6.25 10.75 s busy high width maximum (impulse) t 35 3.5 4.5 6.5 11 s
ad7654 rev. b | page 7 of 28 absolute maximum ratings table 5. parameter values analog inputs inax 1 , inbx 1 , refx, inxn, refgnd avdd + 0.3 v to agnd ? 0.3 v ground voltage differences agnd, dgnd, ognd 0.3 v supply voltages avdd, dvdd, ovdd ?0.3 v to +7 v avdd to dvdd, avdd to ovdd 7 v dvdd to ovdd ?0.3 v to +7 v digital inputs ?0.3 v to dvdd + 0.3 v internal power dissipation 2 700 mw internal power dissipation 3 2.5 w junction temperature 150c storage temperature range ?65c to +150c lead temperature range (soldering 10 sec) 300c 1 see analog inputs section. 2 specification is for device in free air: 48-lead lqfp: ja = 91c/w, jc = 30c/w. 3 specification is for device in free air: 48-lead lfcsp; ja = 26c/w. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. to output pin c l 60pf* 500a i oh 1.6ma i ol 1.4v * in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. 03057-002 figure 2. load circuit fo r digital interface timing (sdout, sync, sclk outputs, c l = 10 pf) 0.8v 2v 2v 0.8v t delay 2v 0.8v t delay 03057-003 figure 3. voltage reference levels for timing esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
ad7654 rev. b | page 8 of 28 pin configuration and fu nction descriptions 48 agnd 47 agnd 46 ina1 45 inan 44 ina2 43 refa 42 refb 41 inb2 40 inbn 39 inb1 38 refgnd 37 ref 35 cnvst 34 pd 33 reset 30 eoc 31 rd 32 cs 36 dvdd 29 busy 28 d15 27 d14 25 d12 26 d13 2 avdd 3 a0 4 byteswap 7 impulse 6 dgnd 5 a/b 1 agnd 8 ser/par 9 d0 10 d1 12 d3/divsclk[1] 11 d2/divsclk[0] 13 d4/ext/int 14 d5/invsync 15 d6/invsclk 16 d7/rdc/sdin 17 ognd 18 ovdd 19 dvdd 20 dgnd 21 d8/sdout 22 d9/sclk 23 d10/sync 24 d11/rderror pin 1 ad7654 top view (not to scale) 03057-004 figure 4. 48-lead lqfp (st-48) and 48-lead lfcsp (cp-48) table 6. pin function descriptions pin no. mnemonic type 1 description 1, 47, 48 agnd p analog power ground pin. 2 avdd p input analog power pin. nominally 5 v. 3 a0 di multiplexer select. when low, the analog inputs ina1 and inb1 are sampled simultaneously, then converted. when high, the analog inputs ina2 and inb2 are sampled simultaneously, then converted. 4 byteswap di parallel mode selection (8 bit, 16 bit). when low, the lsb is output on d[7:0] and the msb is output on d[15:8]. when high, the lsb is output on d[15:8] and the msb is output on d[7:0]. 5 a/ b di data channel selection. in parallel mode, when low, the data from channel b is read. when high, the data from channel a is read. in serial mode, when high, channel a is output first followed by channel b. when low, channel b is output first followed by channel a. 6, 20 dgnd p digital power ground. 7 impulse di mode selection. when high, this input selects a reduced power mode. in this mode, the power dissipation is approximately proportional to the sampling rate. 8 ser/ par di serial/parallel selection input. when low, the parallel port is selected; when high, the serial interface mode is selected and some bits of the data bus are used as a serial port. 9, 10 d[0:1] do bit 0 and bit 1 of the parallel port data output bus. when ser/ par is high, these outputs are in high impedance. 11, 12 d[2:3] or di/o when ser/ par is low, these outputs are used as bit 2 an d bit 3 of the parallel port data output bus. divsclk[0:1] when ser/ par is high, ext/ int is low, and rdc/sdin is low, whic h is the serial master read after convert mode, these inputs, part of the serial port, ar e used to slow down if desired the internal serial clock that clocks the data output. in the othe r serial modes, these inputs are not used. 13 d[4] di/o when ser/ par is low, this output is used as bit 4 of the parallel port data output bus. or ext/ int when ser/ par is high, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock, called respectively, master and slave mode. with ext/ int tied low, the internal clock is sele cted on sclk output. with ext/ int set to a logic high, output data is synchronized to an external clock si gnal connected to the sclk input. 14 d[5] di/o when ser/ par is low, this output is used as bit 5 of the parallel port data output bus. or invsync when ser/ par is high, this input, part of the serial port, is used to select the active state of the sync signal in master modes. when low, sync is ac tive high. when high, sync is active low.
ad7654 rev. b | page 9 of 28 pin no. mnemonic type 1 description 15 d[6] di/o when ser/ par is low, this output is used as bit 6 of the parallel port data output bus. or invsclk when ser/ par is high, this input, part of the serial port, is used to invert the sclk signal. it is active in both master and slave modes. 16 d[7] di/o when ser/ par is low, this output is used as bit 7 of the parallel port data output bus. or rdc/sdin when ser/ par is high, this input, part of the serial port, is used as either an ex ternal data input or a read mode selection input, depending on the state of ext/ int . when ext/ int is high, rdc/sdin can be used as a data input to daisy-chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on sdout with a delay of 32 sclk periods after the initiation of the read sequence. when ext/ int is low, rdc/sdin is used to select the read mode. when rdc/sdin is high, the previous data is output on sdout during conversion . when rdc/sdin is low, the data can be output on sdout only when the conversion is complete. 17 ognd p input/output interface digital power ground. 18 ovdd p input/output interface digital power. nominally at th e same supply as the supply of the host interface (5 v or 3 v). 19, 36 dvdd p digital power. nominally at 5 v. 21 d[8] do when ser/ par is low, this output is used as bit 8 of the parallel port data output bus. or sdout when ser/ par is high, this output, part of the serial port, is used as a serial data output synchronized to sclk. conversion results are stored in a 32-bit on-chip register. the ad7654 provides the two conversion results, msb first, from its internal shift register. the order of channel outputs is controlled by a/ b . in serial mode, when ext/ int is low, sdout is valid on both edges of sclk. in serial mode, when ext/ int is high: if invsclk is low, sdout is updated on the sclk rising edge and valid on the next falling edge. if invsclk is high, sdout is updated on the sclk falling edge and valid on the next rising edge. 22 d[9] di/o when ser/ par is low, this output is used as bit 9 of the parallel port data output bus. or sclk when ser/ par is high, this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the ext/ int pin. the active edge where the data sdout is updated depends on the logic state of the invsclk pin. 23 d[10] do when ser/ par is low, this output is used as bit 10 of the parallel port data output bus. or sync when ser/ par is high, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (ext/ int = logic low). when a read sequence is initiated and invsync is lo w, sync is driven high and frames sdout. after the first channel is output, sync is pulsed low. when a read sequence is initiated and invsync is high, sync is driven low and remains low while sdout output is valid. after the first channel is output, sync is pulsed high. 24 d[11] do when ser/ par is low, this output is used as bit 11 of the parallel port data output bus. or rderror when ser/ par is high and ext/ int is high, this output, part of the serial port, is used as an incomplete read error flag. in slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and rderror is pulsed high. 25 to 28 d[12:15] do bit 12 to bit 15 of the parallel port data output bus. when ser/ par is high, these outputs are in high impedance. 29 busy do busy output. transitions high when a conversion is started and remains high until the two conversions are complete and the data is latched into the on-chip shift register. the falling edge of busy can be used as a data ready clock signal. 30 eoc do end of convert output. goes low at each channel conversion. 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the ex ternal serial clock. 33 reset di reset input. when set to a logic high, reset the ad 7654. current conversion if any is aborted. if not used, this pin could be tied to dgnd. 34 pd di power-down input. when set to a logic high, power consumption is reduced and conversions are inhibited after the current one is completed.
ad7654 rev. b | page 10 of 28 pin no. mnemonic type 1 description 35 cnvst di start conversion. a falling edge on cnvst puts the internal sample-and-hold into the hold state and initiates a conversion. in impulse mode (impulse = high), if cnvst is held low when the acquisition phase (t 8 ) is complete, the internal sample-and-hold is put into the hold state and a conversion is immediately started. 37 ref ai this input pin is used to provide a reference to the converter. 38 refgnd ai reference input analog ground. 39, 41 inb1, inb2 ai channel b analog inputs. 40, 45 inbn, inan ai analog inputs ground senses . allow to sense each channel ground independently. 42, 43 refb, refa ai these inputs are the referenc es applied to channel a and channel b, respectively. 44, 46 ina2, ina1 ai channel a analog inputs. 1 ai = analog input; di = digital input; di/o = bidirectional digital; do = digital output; p = power.
ad7654 rev. b | page 11 of 28 terminology integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. full-scale error the last transition (from 111. . .10 to 111. . .11) should occur for an analog voltage 1? lsb below the nominal full scale (4.999886 v for the 0 v to 5 v range). the full-scale error is the deviation of the actual level of the last transition from the ideal level. unipolar zero error the first transition should occur at a level ? lsb above analog ground (76.29 v for the 0 v to 5 v range). the unipolar zero error is the deviation of the actual transition from that point. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. signal-to-noise and distortion ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. spurious-free dynamic range (sfdr) the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad and expressed in bits by enob = ((sinad db ? 1.76)/6.02) and is expressed in bits. aperture delay aperture delay is a measure of acquisition performance and is measured from the falling edge of the cnvst input to when the input signals are held for a conversion. transient resp onse the time required for the ad7654 to achieve its rated accuracy after a full-scale step function is applied to its input.
ad7654 rev. b | page 12 of 28 typical performance characteristics code ?1 inl (lsb) ?5 ?3 65535 0 ?2 ?4 32768 16384 49152 0 1 2 3 4 5 03057-005 figure 5. integral nonlinearity vs. code code in hex 7fbf 0 counts 8000 6000 4000 2000 0 7000 3000 1000 5000 7fc0 0 7fc1 14 7fc2 953 7fc3 7288 7fc4 7220 7fc5 903 7fc6 6 7fc7 0 7fc8 0 03057-006 figure 6. histogram of 16,384 conversions of a dc input at the code transition frequency (khz) ?120 amplitude (db of full scale) ?160 150 0 ?140 100 50 125 ?100 ?80 ?60 ?40 ?20 0 25 75 175 200 225 250 8192 point fft f s = 500khz f in = 100khz, ?0.5db snr = 89.9db sinad = 89.4db thd = ?99.3db 03057-007 figure 7. fft plot code dnl (lsb) ?3 0 ?2 16384 32768 ?1 0 1 2 3 49152 65535 03057-008 figure 8. differential nonlinearity vs. code code in hex 8000 7fc0 0 counts 7000 4000 2000 0 6000 3000 1000 5000 7fc1 7fc2 7fc3 176 7fc4 7fc5 132 7fc6 7fc7 00 7fbf 0 9366 9000 10000 3411 3299 03057-009 figure 9. histogram of 16,384 conversions of a dc input at the code center temperature (c) 96 snr (db) 84 90 25 125 ?55 93 87 ?35 65 45 5 105 ?15 85 ? 98 thd (db) ?106 ?102 ?100 ?104 snr thd 03057-010 figure 10. snr, thd vs. temperature
ad7654 rev. b | page 13 of 28 frequency (khz) 100 snr, sinad (db) 90 70 80 10 1000 1 100 95 85 75 16.0 enob (bits) 15.0 13.0 14.0 15.5 14.5 13.5 snr sinad enob 03057-011 figure 11. snr, sinad, and enob vs. frequency input level (db) 92 snr, sinad (db) 90 86 88 ?40 ?20 ?60 ?30 ?50 ?10 0 snr sinad 03057-012 figure 12. snr and sinad vs. input level (referred to full scale) frequency (khz) thd, harmonics, crosstalk (db) ?115 ?105 10 1000 1 100 ?110 90 sfdr (db) 80 60 70 85 75 65 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ? 60 95 100 105 110 115 sfdr crosstalk b to a crosstalk a to b thd third harmonic second harmonic 03057-013 figure 13. thd, harmonics, crosstalk, and sfdr vs. frequency temperature (c) lsb ?10 ?15 ?55 25 ?35 5 45 ?8 ?6 ?4 ?2 0 2 4 6 8 10 65 85 105 125 full-scale error zero error 03057-014 figure 14. full-scale error and zero error vs. temperature operating currents (ma) 10 1 0.1 100 sampling rate (ksps) 10 100 1000 1 normal avdd normal dvdd impulse avdd ovdd 2.7v 0.01 0.001 0.0001 impulse dvdd 03057-015 figure 15. operating currents vs. sample rate c l (pf) 50 t 18 delay (ns) 20 0 10 100 200 0 150 50 30 40 ovdd = 2.7v @ 85c ovdd = 2.7v @ 25c ovdd = 5v @ 85c ovdd = 5v @ 25c 03057-016 figure 16. typical delay vs. load capacitance c l
ad7654 rev. b | page 14 of 28 application information circuit information the ad7654 is a very fast, low power, single-supply, precise, simultaneous sampling 16-bit adc. the ad7654 provides the user with two on-chip, track-and- hold, successive approximation adcs that do not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. the ad7654 can also be used as a 4-channel adc with two pairs simultaneously sampled. the ad7654 can be operated from a single 5 v supply and be interfaced to either 5 v or 3 v digital logic. it is housed in a 48-lead lqfp or tiny 48-lead lfcsp that combines space savings and allows flexible configurations as either a serial or parallel interface. the ad7654 is pin-to-pin compatible with pulsar adcs. modes of operation the ad7654 features two modes of operation, normal and impulse. each of these modes is more suitable for specific applications. normal mode is the fastest mode (500 ksps). except when it is powered down (pd = high), the power dissipation is almost independent of the sampling rate. impulse mode, the lowest power dissipation mode, allows power saving between conversions. the maximum throughput in this mode is 444 ksps. when operating at 10 ksps, for example, it typically consumes only 2.6 mw. this feature makes the ad7654 ideal for battery-powered applications. transfer functions the ad7654 data format is straight binary. the ideal transfer characteristic for the ad7654 is shown in figure 17 and tabl e 7 . the lsb size is 2*v ref /65536, which is about 76.3 v. 000...000 000...001 000...010 111...101 111...110 111...111 analog input +fs ? 1.5 lsb +fs ? 1 lsb ?fs + 1 lsb ?fs ?fs + 0.5 lsb adc code (straight binary) 03057-017 figure 17. adc ideal transfer function table 7. output codes and ideal input voltages description analog input v ref = 2.5 v digital output code fsr ? 1 lsb 4.999924 v 0xffff 1 fsr ? 2 lsb 4.999847 v 0xfffe midscale + 1 lsb 2.500076 v 0x8001 midscale 2.5 v 0x8000 midscale ? 1 lsb 2.499924 v 0x7fff ?fsr + 1 lsb ?76.29 v 0x0001 ?fsr 0 v 0x0000 2 1 this is also the code fo r overrange analog input (v inx C v inxn above 2 (v ref ? v refgnd )). 2 this is also the code fo r underrange analog input (v inx below v inxn ).
ad7654 rev. b | page 15 of 28 avdd agnd dgnd dvdd ovdd ognd ser/par cnvst busy sdout sclk rd cs reset pd refgnd c ref 2.5v ref note 1 ref ref a ref b 30 ? d clock ad7654 c/p/ dsp serial port digital supply (3.3v or 5v) analog supply (5v) dvdd a/b note 7 byteswap d v dd 50k ? 100nf 1m ? ina1 c c 2.7nf u1 note 4 note 5 50? + 10 ? 2.7nf u2 note 4 note 5 50? + 10? inan ina2 note 2 note 3 note 6 ad780 10f 100nf + 100nf + 100nf + 10f 50 ? + notes 1. see voltage reference input section. 2. with the recommended voltage references, c ref is 47f. see voltage reference input section. 3. optional circuitry for hardware gain calibration. 4. the ad8021 is recommended. see driver amplifier choice section. 5. see analog inputs section. 6. optional, see power supply section. 7. optional low jitter cnvst. see conversion control section. a0 inb1 2.7nf u3 note 4 note 5 50? + 10 ? inbn 2.7nf u4 note 4 note 5 50? + 10? inb2 analog input a1 analog input a2 analog input b1 a n a log input b2 c c c c c c 10f 1f 03057-018 note 1 ? ? ? ? figure 18. typical connection diagram (serial interface)
ad7654 rev. b | page 16 of 28 typical connection diagram figure 18 shows a typical connection diagram for the ad7654. different circuitry shown on this diagram is optional and is discussed in the following sections. analog inputs figure 19 shows a simplified analog input section of the ad7654. ina1 r a inb2 c s c s agnd a v dd ina2 inan inbn inb1 r b 03057-019 a0 a0 = l a0 = l a0 = h a0 = h figure 19. simplified analog input the diodes shown in figure 19 provide esd protection for the inputs. care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs. this causes these diodes to become forward biased and start conducting current. these diodes can handle a forward-biased current of 120 ma maximum. this condition could eventually occur when the input buffers (u1) or (u2) supplies are different from avdd. in such a case, an input buffer with a short-circuit current limitation can be used to protect the part. this analog input structure allows the sampling of the differential signal between inx and inxn. unlike other converters, the inxn is sampled at the same time as the inx input. by using these differential inputs, small signals common to both inputs are rejected. during the acquisition phase, for ac signals, the ad7654 behaves like a one-pole rc filter consisting of the equivalent resistance r a , r b , and c s . the resistors r a and r b are typically 500 and are a lumped component made up of some serial resistors and the on resistance of the switches. the capacitor c s is typically 32 pf and is mainly the adc sampling capacitor. this one-pole filter with a typical ?3 db cutoff frequency of 10 mhz reduces undesirable aliasing effects and limits the noise coming from the inputs. because the input impedance of the ad7654 is very high, the ad7654 can be driven directly by a low impedance source without gain error. to further improve the noise filtering of the ad7654 analog input circuit, an external one-pole rc filter between the amplifier output and the adc input, as shown in figure 18 , can be used. however, the source impedance has to be kept low because it affects the ac performance, especially the total harmonic distortion. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd degrades as the source impedance increases. input channel multiplexer the ad7654 allows the choice of simultaneously sampling the inputs pairs ina1/inb1 or ina2/inb2 with the a0 multiplexer input. when a0 is low, the input pairs ina1/inb1 are selected, and when a0 is high, the input pairs ina2/inb2 are selected. note that inax is always converted before inbx regardless of the state of the digital interface channel selection a/ b pin. also, note that the channel selection control a0 should not be changed during the acquisition phase of the converter. refer to the conversion control section and figure 22 for timing details. driver amplifier choice although the ad7654 is easy to drive, the driver amplifier needs to meet at least the following requirements: ? for multichannel, multiplexed applications, the driver amplifier and the ad7654 analog input circuit together must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). in the amplifiers data sheet, the settling at 0.1% or 0.01% is more commonly specified. it could significantly differ from the settling time at a 16-bit level and, therefore, it should be verified prior to the driver selection. ? the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transition noise performance of the ad7654. the noise coming from the driver is filtered by the ad7654 analog input circuit one- pole low-pass filter made by r a , r b , and c s . the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 db3 2 )( 2 56 56 log20 n loss nef snr where: f C3 db is the C3 db input bandwidth in mhz of the ad7654 (10 mhz) or the cutoff frequency of the input filter, if any is used. n is the noise factor of the amplifier (1 if in buffer configuration). e n is the equivalent input noise voltage of the op amp in nv/hz. for instance, a driver like the ad8021 with an equivalent input noise of 2 nv/hz, configured as a buffer, and thus with a noise gain of +1, degrades the snr by only 0.06 db with the filter in figure 18 , and by 0.10 db without. ? the driver needs to have a thd performance suitable to that of the ad7654.
ad7654 rev. b | page 17 of 28 the ad8021 meets these requirements and is usually appro- priate for almost all applications. the ad8021 needs an external compensation capacitor of 10 pf. this capacitor should have good linearity as an npo ceramic or mica type. the ad8022 could be used where a dual version is needed and a gain of +1 is used. the ad829 is another alternative where high frequency (above 100 khz) performance is not required. in a gain of +1, it requires an 82 pf compensation capacitor. the ad8610 is another option where low bias current is needed in low frequency applications. refer to table 8 for some recommended op amps. table 8. recommended driver amplifiers amplifier typical application ada4841 very low noise, low distortion, low power, low frequency ad829 very low noise, low frequency ad8021 very low noise, high frequency ad8022 very low noise, high frequency, dual ad8655/ad8656 low noise, 5 v single supply, low power, low frequency, single/dual ad8610/ad8620 low bias current, low frequency, single/dual voltage reference input the ad7654 requires an external 2.5 v reference. the reference input should be applied to ref, refa, and refb. the voltage reference input ref of the ad7654 has a dynamic input impedance; it should therefore be driven by a low impedance source with an efficient decoupling. this decoupling depends on the choice of the voltage reference but usually consists of a 1 f ceramic capacitor and a low esr tantalum capacitor connected to the refa, refb, and refgnd inputs with minimum parasitic inductance. a value of 47 f is an appro- priate value for the tantalum capacitor when using one of the recommended reference voltages: ? the low noise, low temperature drift ad780, ad361, adr421, and adr431 voltage reference. ? the low cost ad1582 voltage reference. for applications using multiple ad7654s with one voltage reference source, it is recommended that the reference source drives each adc in a star configuration with individual decoupling placed as close as possible to the ref/refgnd inputs. also, it is recommended that a buffer, such as the ad8031/ad8032 , be used in this configuration. care should be taken with the reference temperature coefficient of the voltage reference, which directly affects the full-scale accuracy if this parameter is applicable. for instance, a 15 ppm/c tempco of the reference changes the full-scale accuracy by 1 lsb/c. power supply the ad7654 uses three sets of power supply pins: an analog 5 v supply avdd, a digital 5 v core supply dvdd, and a digital input/output interface supply ovdd. the ovdd supply allows direct interface with any logic working between 2.7 v and dvdd + 0.3 v. to reduce the number of supplies needed, the digital core (dvdd) can be supplied through a simple rc filter from the analog supply, as shown in figure 18 . the ad7654 is independent of power supply sequencing, once ovdd does not exceed dvdd by more than 0.3 v, and thus free from supply voltage induced latch-up. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 20 . frequency (khz) 40 psrr (db) 100 1000 10000 45 50 55 60 65 70 10 1 03057-020 figure 20. psrr vs. frequency power dissipation in impulse mode, the ad7654 automatically reduces its power consumption at the end of each conversion phase. during the acquisition phase, the operating currents are very low, which allows significant power savings when the conversion rate is reduced, as shown in figure 21 . this feature makes the ad7654 ideal for very low power battery applications. note that the digital interface remains active even during the acquisition phase. to reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (that is, dvdd and dgnd), and ovdd should not exceed dvdd by more than 0.3 v.
ad7654 rev. b | page 18 of 28 sampling rate (ksps) 0.1 power dissip a tion (mw) 100 1000 1 10 100 1000 normal impulse 03057-021 10 1 figure 21. power dissipa tion vs. sample rate conversion control figure 22 shows the detailed timing diagrams of the conversion process. the ad7654 is controlled by the signal cnvst , which initiates conversion. once initiated, it cannot be restarted or aborted, even by the power-down input, pd, until the conversion is complete. the cnvst signal operates independently of the cs and rd signals. busy acquire t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 convert a acquire convert convert b t 12 a0 t 14 t 15 t 13 t 11 t 10 eoc cnvst 03057-022 mode figure 22. basic conversion timing although cnvst is a digital signal, it should be designed with special care with fast, clean edges and levels, and with minimum overshoot and undershoot or ringing. for applications where the snr is critical, the cnvst signal should have very low jitter. some solutions to achieve this are to use a dedicated oscillator for cnvst generation or, at least, to clock it with a high frequency, low jitter clock, as shown in figure 18 . in impulse mode, conversions can be automatically initiated. if cnvst is held low when busy is low, the ad7654 controls the acquisition phase and automatically initiates a new conversion. by keeping cnvst low, the ad7654 keeps the conversion process running by itself. note that the analog input has to be settled when busy goes low. also, at power-up, cnvst should be brought low once to initiate the conversion process. in this mode, the ad7654 could sometimes run slightly faster than the guaranteed limits of 444 ksps in impulse mode. this feature does not exist in normal mode. digital interface the ad7654 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. the serial interface is multiplexed on the parallel data bus. the ad7654 digital interface accommodates either 3 v or 5 v logic by simply connecting the ovdd supply pin of the ad7654 to the host system interface digital supply. the two signals cs and rd control the interface. when at least one of these signals is high, the interface outputs are in high impedance. usually, cs allows the selection of each ad7654 in multicircuit applications and is held low in a single ad7654 design. rd is generally used to enable the conversion result on the data bus. in parallel mode, signal a/ b allows the choice of reading either the output of channel a or channel b, whereas in serial mode, signal a/ b controls which channel is output first. figure 23 details the timing when using the reset input. note the current conversion, if any, is aborted and the data bus is high impedance while reset is high. t 9 reset data bus busy t 8 cnvst 03057-023 figure 23. reset timing parallel interface the ad7654 is configured to use the parallel interface when ser/ par is held low. master parallel interface data can be read continuously by tying cs and rd low, thus requiring minimal microprocessor connections. however, in this mode, the data bus is always driven and cannot be used in shared bus applications (unless the device is held in reset). figure 24 details the timing for this mode.
ad7654 rev. b | page 19 of 28 t 1 t 3 t 4 t 17 busy data bus t 16 new a or b previous channel a or b previous channel b or new a t 10 cs = rd = 0 eoc cnvst 03057-024 figure 24. master parallel data timing for continuous read slave parallel interface in slave parallel reading mode, the data can be read either after each conversion, which is during the next acquisition phase or during the other channels conversion, or during the following conversion, as shown in figure 25 and figure 26 , respectively. when the data is read during the conversion, however, it is recommended that it is read only during the first half of the conversion phase. this avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. data bus t 18 t 19 busy current conversion cs rd 03057-025 figure 25. slave parallel data timing for a read after conversion previous conversion t 1 t 3 t 18 t 19 t 4 busy data bus t 13 t 11 t 12 t 10 cs =0 eoc cnvst, rd 03057-026 figure 26. slave parallel data timing for a read during conversion 8-bit interface (master or slave) the byteswap pin allows a glueless interface to an 8-bit bus. as shown in figure 27 , the lsb byte is output on d[7:0] and the msb is output on d[15:8] when byteswap is low. when byteswap is high, the lsb and msb bytes are swapped, the lsb is output on d[15:8], and the msb is output on d[7:0]. by connecting byteswap to an address line, the 16-bit data can be read in two bytes on either d[15:8] or d[7:0]. byteswap pins d[15:8] pins d[7:0] hi-z hi-z high byte low byte low byte high byte hi-z hi-z t 18 t 18 t 19 cs rd 03057-027 figure 27. 8-bit parallel interface channel a/ b output the a/ b input controls which channels conversion results (inax or inbx) are output on the data bus. the functionality of a/ b is detailed in figure 28 . when high, the data from channel a is available on the data bus. when low, the data from channel b is available on the bus. note that channel a can be read immediately after conversion is done ( eoc ), while channel b is still in its converting phase. however, in any of the serial reading modes, channel a data is updated only after channel b is converted. t 18 t 20 cs data bus rd hi-z a/b hi-z channel a channel b 03057-028 figure 28. a/ b channel reading
ad7654 rev. b | page 20 of 28 serial interface the ad7654 is configured to use the serial interface when the ser/ par is held high. the ad7654 outputs 32 bits of data, msb first, on the sdout pin. the order of the channels being output is also controlled by a/ b . when high, channel a is output first; when low, channel b is output first. this data is synchronized with the 32 clock pulses provided on the sclk pin. master serial interface internal clock the ad7654 is configured to generate and provide the serial data clock sclk when the ext/ int pin is held low. the ad7654 also generates a sync signal to indicate to the host when the serial data is valid. the serial clock sclk and the sync signal can be inverted if desired. the output data is valid on both the rising and falling edge of the data clock. depending on rdc/sdin input, the data can be read after each conversion or during the following conversion. figure 29 and figure 30 show the detailed timing diagrams of these two modes. usually, because the ad7654 is used with a fast throughput, the master-read-during-convert mode is the most recommended serial mode when it can be used. in this mode, the serial clock and data toggle at appropriate instants, which minimizes potential feedthrough between digital activity and the critical conversion decisions. the sync signal goes low after the lsb of each channel has been output. note that in this mode, the sclk period changes because the lsbs require more time to settle, and the sclk is derived from the sar conversion clock. note that in the master-read-after-convert mode, unlike in other modes, the signal busy returns low after the 32 data bits are pulsed out and not at the end of the conversion phase, which results in a longer busy width. one advantage of using this mode is that it can accommodate slow digital hosts because the serial clock can be slowed down by using divsclk[1:0] inputs. refer to table 4 for the timing details.
ad7654 rev. b | page 21 of 28 t 3 busy sync sclk sdout 1216 31 32 ch a d14 ch b d15 ch b d1 x rdc/sdin = 0 invsclk = in vsync = 0 t 21 t 23 t 30 t 36 t 25 t 28 t 32 t 31 t 33 t 34 t 12 17 t 35 t 26 ext/int = 0 a/b = 1 cnvst cs, rd eoc 03057-029 t 11 t 13 t 10 t 26 t 27 t 22 t 29 ch b d0 ch a d0 t 37 ch a d15 figure 29. master serial data timing for reading (read after conversion) rdc/sdin = 1 invsclk = invsync = 0 t 3 t 1 t 24 t 21 t 26 t 27 t 28 t 31 t 33 t 32 t 34 t 30 t 29 t 23 t 22 ch a d15 x 12 16 1 2 t 25 busy sync sclk sdout 16 ch b d15 ch a d0 ch a d14 ch b d14 ch b d0 t 10 t 11 t 13 t 12 ext/int = 0 a/b = 1 cnvst cs, rd eoc 03057-030 figure 30. master serial data timing for reading (read previous conversion during convert)
ad7654 rev. b | page 22 of 28 slave serial interface external clock the ad7654 is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int pin is held high. in this mode, several methods can be used to read the data. the external serial clock is gated by cs . when both cs and rd are low, the data can be read after each conversion or during the following conversion. the external clock can be either a continuous or discontinuous clock. a discontinuous clock can be either normally high or normally low when inactive. figure 32 and figure 33 show the detailed timing diagrams of these methods. while the ad7654 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. this is particularly important during the second half of the conversion phase of each channel because the ad7654 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. for this reason, it is recommended that when an external clock is provided, it is a discontinuous clock that toggles only when busy is low or, more importantly, that it does not transition during the latter half of eoc high. external discontinuous cloc k data read after convert although the maximum throughput cannot be achieved in this mode, it is the most recommended of the serial slave modes. figure 32 shows the detailed timing diagrams of this method. after a conversion is complete, indicated by busy returning low, the conversion results can be read while both cs and rd are low. data is shifted out from both channels msb first, with 32 clock pulses and is valid on both rising and falling edges of the clock. one advantage of this method is that conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. another advantage is the ability to read the data at any speed up to 40 mhz, which accommodates both a slow digital host interface and the fastest serial reading. finally, in this mode only, the ad7654 provides a daisy-chain feature using the rdc/sdin (serial data in) input pin for cascading multiple converters together. this feature is useful for reducing c omponent count and wiring connections when it is desired, as in isolated multiconverter applications. an example of the concatenation of two devices is shown in figure 31 . simultaneous sampling is possible by using a common cnvst signal. note that the rdc/sdin input is latched on the edge of sclk opposite the one used to shift out the data on sdout. therefore, the msb of the upstream converter follows the lsb of the downstream converter on the next sclk cycle. the sdin input should be tied either high or low on the most upstream converter in the chain. busy busy ad7654 #2 (upstream) ad7654 #1 (downstream) rdc/sdin sdout cnvst cs sclk rdc/sdin sdout cnvst cs sclk data out sclk in cs in c nvst in busy out 03057-031 figure 31. two ad7654s in a daisy-chain configuration external clock data read previous during convert figure 33 shows the detailed timing diagrams of this method. during a conversion, while both cs and rd are low, the result of the previous conversion can be read. the data is shifted out msb first with 32 clock pulses and is valid on both the rising and falling edges of the clock. the 32 bits have to be read before the current conversion is completed; otherwise, rderror is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. there is no daisy-chain feature in this mode, and rdc/sdin input should always be tied either high or low. to reduce performance degradation due to digital activity, a fast discontinuous clock (at least 32 mhz in impulse mode and 40 mhz in normal mode) is recommended to ensure that all of the bits are read during the first half of each conversion phase ( eoc high, t 11 , t 12 ). it is also possible to begin to read data after conversion and continue to read the last bits after a new conversion has been initiated. this allows the use of a slower clock speed like 26 mhz in impulse mode and 30 mhz in normal mode.
ad7654 rev. b | page 23 of 28 cs sclk sdout ch a d15 busy sdin invsclk = 0 t 42 t 43 t 44 t 38 t 39 t 23 t 40 t 41 x 123 3031323334 ext/int = 1 ch b d0 ch b d1 ch a d13 ch a d14 xcha d14 xcha d15 xcha d13 xcha d14 xchb d0 xchb d1 ycha d14 ycha d15 rd = 0 a/b = 1 eoc 03057-032 xcha d15 figure 32. slave serial data timing for reading (read after convert) cnvst sdout sclk x chad15 123 3132 t 3 t 42 t 43 t 44 t 38 t 39 t 23 busy in v sclk = 0 cs ext/int = 1 chbd0 chbd1 chad13 chad14 rd = 0 eoc t 10 t 11 t 13 t 12 a / b=1 03057-033 figure 33. slave serial data timing for reading (read previous conversion during convert)
ad7654 rev. b | page 24 of 28 microprocessor interfacing the ad7654 is ideally suited for traditional dc measurement applications supporting a microprocessor and for ac signal processing applications interfacing to a digital signal processor. the ad7654 is designed to interface with either a parallel 8-bit wide or 16-bit wide interface, a general-purpose serial port, or i/o ports on a microcontroller. a variety of external buffers can be used with the ad7654 to prevent digital noise from coupling into the adc. the following section illustrates the use of the ad7654 with an spi-equipped dsp, the adsp-219x. spi interface (adsp-219 x ) figure 34 shows an interface diagram between the ad7654 and the spi equipped adsp-219x. to accommodate the slower speed of the dsp, the ad7654 acts as a slave device and data must be read after conversion. this mode also allows the daisy- chain feature. the convert command can be initiated in response to an internal timer interrupt. the 32-bit output data is read with two serial peripheral interface (spi) 16-bit wide accesses. the reading process can be initiated in response to the end-of-conversion signal (busy going low) using an interrupt line of the dsp. by writing to the spi control register (spicltx), the serial interface (spi) on the adsp-219x is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, clock phase bit (cpha) = 1, and spi interrupt enable (timod) = 00. to meet all timing requirements, the spi clock should be limited to 17 mbps, which allows it to read an adc result in less than 1 s. when a higher sampling rate is desired, use of one of the parallel interface modes is recommended. ad7654* adsp-219x* ser/par pfx misox sckx pfx or tfsx busy sdout sclk cnvst ext/int cs rd invsclk d v dd *additional pins omitted for clarity spixsel (pfx) 0 3057-034 figure 34. interfacing the ad7654 to an spi interface
ad7654 rev. b | page 25 of 28 application hints layout the ad7654 has very good immunity to noise on the power supplies. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the ad7654 should be designed so the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. digital and analog ground planes should be joined in only one place, preferably underneath the ad7654, or as close as possible to the ad7654. if the ad7654 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at only a star ground point established as close as possible to the ad7654. running digital lines under the device should be avoided because these couple noise onto the die. the analog ground plane should be allowed to run under the ad7654 to avoid noise coupling. fast switching signals like cnvst or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on different but close layers of the board should run at right angles to each other. this reduces the effect of crosstalk through the board. the power supply lines to the ad7654 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also important to lower the supplys impedance presented to the ad7654 and to reduce the magnitude of the supply spikes. decoupling ceramic capacitors, typically 100 nf, should be placed on each power supply pinavdd, dvdd, and ovddclose to, and ideally right up against these pins and their corresponding ground pins. additionally, low esr 10 f capacitors should be located near the adc to further reduce low frequency ripple. the dvdd supply of the ad7654 can be a separate supply or can come from the analog supply avdd or the digital interface supply ovdd. when the system digital supply is noisy or when fast switching digital signals are present, if no separate supply is available, the user should connect dvdd to avdd through an rc filter (see figure 18 ) and the system supply to ovdd and the remaining digital circuitry. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. the ad7654 has five different ground pins: ingnd, refgnd, agnd, dgnd, and ognd. ingnd is used to sense the analog input signal. refgnd senses the reference voltage and, because it carries pulsed currents, should be a low impedance return to the reference. agnd is the ground to which most internal adc analog signals are referenced; it must be connected with the least resistance to the analog ground plane. dgnd must be tied to the analog or digital ground plane, depending on the configuration. ognd is connected to the digital system ground. evaluating the ad7654 performance a recommended layout for the ad7654 is outlined in the documentation of the evaluation board for the eval-ad7654cb . the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control-brd3 .
ad7654 rev. b | page 26 of 28 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 7.00 bsc sq 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 figure 35. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters compliant to jedec standards mo-220-vkkd-2 pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane paddle connected to agnd. this connection is not required to meet the electrical performances 0.25 min 0.20 ref exposed pad (bottom view) figure 36. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm (cp-48-1) dimensions shown in millimeters
ad7654 rev. b | page 27 of 28 ordering guide model temperature range package description package option ad7654acp C40c to +85c lead frame chip scale package [lfcsp_vq] cp-48-1 ad7654acprl C40c to +85c lead frame chip scale package [lfcsp_vq] cp-48-1 ad7654acpz 1 C40c to +85c lead frame chip scale package [lfcsp_vq] cp-48-1 ad7654acpzrl 1 C40c to +85c lead frame chip scale package [lfcsp_vq] cp-48-1 ad7654ast C40c to +85c low profile quad flat package [lqfp] st-48 ad7654astrl C40c to +85c low profile quad flat package [lqfp] st-48 ad7654astz 1 C40c to +85c low profile quad flat package [lqfp] st-48 ad7654astzrl 1 C40c to +85c low profile quad flat package [lqfp] st-48 eval-ad7654cb 2 evaluation board eval-control brd2 3 controller board eval-control brd3 3 controller board 1 z = pb free part. 2 this board can be used as a standalone evaluation board or in conjunction with the eval-control-brd2/eval-control-brd3 for eva luation/demonstration purposes. 3 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designator.
ad7654 rev. b | page 28 of 28 notes ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c03057C0C11/05(b)

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